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? 1997 microchip technology inc. preliminary ds21203a-page 1 m 24aa256/24lc256/24C256 device selection table features low power cmos technology - maximum write current 3 ma at 5.5v - maximum read current 400 m a at 5.5v - standby current 500 na typical at 5.5v 2-wire serial interface bus, i 2 c compatible cascadable for up to eight devices self-timed erase/write cycle 64-byte page-write mode available fast write cycle time in byte or page mode - 5 ms max for 24lc256 and 24C256 - 10 ms max for 24aa256 hardware write protect for entire array schmitt trigger inputs for noise suppression 1,000,000 erase/write cycles guaranteed electrostatic discharge protection > 4000v data retention > 200 years 8-pin pdip and soic (208 mil) packages temperature ranges: description the microchip technology inc. 24aa256/24lc256/ 24C256 (24xx256*) is a 32k x 8 (256k bit) serial elec- trically erasable prom, capable of operation across a broad voltage range (1.8v to 5.5v). it has been devel- oped for advanced, low power applications such as per- sonal communications or data acquisition. this device also has a page-write capability of up to 64 bytes of data. this device is capable of both random and sequential reads up to the 256k boundary. functional address lines allow up to eight devices on the same bus, for up to 2mbit address space. this device is avail- able in the standard 8-pin plastic dip, and 8-pin soic (208 mil) packages. package type block diagram part number v cc range max clock frequency temp ranges 24aa256 1.8-5.5v 400 khz ? c,i 24lc256 2.5-5.5v 400 khz c,i 24C256 4.5-5.5v 400 khz c,i,e ? 100 khz for v cc < 2.5v. 100 khz for e temperature range. - commercial (c): 0 c to +70 c - industrial (i): -40 c to +85 c - automotive (e): -40 c to +125 c a0 a1 a2 vss vcc wp scl sda 1 2 3 4 8 7 6 5 24xx256 8-pin pdip a0 a1 a2 v ss v cc wp scl sda 24xx256 1 2 3 4 8 7 6 5 8-pin soic hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic i/o control logic a0?2 sda scl v cc v ss wp i/o write protect circuitry 256k i 2 c cmos serial eeprom i 2 c is a trademark of philips corporation. *24xx256 is used in this document as a generic part number for the 24aa256/24lc256/24C256 devices.
24aa256/24lc256/24C256 ds21203a -page 2 preliminary ? 1997 microchip technology inc. 1.0 electrical chara cteristics 1.1 maxim um ratings* v cc ................................................................................................. 7.0v all inputs and outputs w .r .t. v ss ............................. -0.6v to v cc +1.0v stor age temper ature ................................................... -65 c to +150 c ambient temp . with po w er applied ............................... -65 c to +125 c solder ing temper ature of leads (10 seconds) ........................... +300 c esd protection on all pins ................................................................. 3 4 kv *notice: stresses abo v e those listed under ?axim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ational listings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per i- ods ma y aff ect de vice reliability . t able 1-1 pin function t ab le figure 1-1: bus timing data name function a0, a1, a2 user con gur ab le chip selects v ss ground sd a ser ial data scl ser ial cloc k wp wr ite protect input v cc +1.8 to 5.5v ( 24aa256 ) +2.5 to 5.5v ( 24lc256 ) +4.5 to 5.5v ( 24C256 ) t able 1-2 dc characteristics all par ameters apply across the speci ed oper ating r anges unless otherwise noted. commercial (c): v cc = +1.8v to 5.5v t amb = 0 c to +70 c industr ial (i): v cc = +1.8v to 5.5v t amb = -40 c to +85 c a utomotiv e (e): v cc = +4.5v to 5.5v t amb = -40 c to 125 c p arameter symbol min max units conditions a0, a1, a2, scl, sd a, and wp pins: high le v el input v oltage v ih 0.7 v cc v lo w le v el input v oltage v il 0.3 v cc v hysteresis of schmitt t r igger inputs (sd a, scl pins) v hys 0.05 v cc v v cc 3 2.5v (note) lo w le v el output v oltage v ol 0.40 v i ol = 3.0 ma @ v cc = 4.5v i ol = 2.1 ma @ v cc = 2.5v input leakage current i li -10 10 m a v in = v ss or v cc , wp = v ss v in = v ss or v cc , wp = v cc output leakage current i lo -10 10 m a v out = v ss or v cc pin capacitance (all inputs/outputs) c in , c out 10 pf v cc = 5.0v (note) t amb = 25?c , f c = 1 mhz oper ating current i cc wr ite 3 ma v cc = 5.5v i cc read 400 m a v cc = 5.5v , scl = 400 khz standb y current i ccs 1 m a scl = sd a = v cc = 5.5v a0, a1, a2, wp = v ss note: this par ameter is per iodically sampled and not 100% tested. wp (unprotected) (protected) t su : wp t hd : wp scl sd a in t su : sta sd a out t hd : sta t low t high t r t buf t aa t hd : dat t su : dat t su : sto t sp t f v hys
24aa256/24lc256/24C256 ? 1997 microchip technology inc. preliminary ds21203a -page 3 t able 1-3 a c c haracteristics all par ameters apply across the spec- i ed oper ating r anges unless other- wise noted commercial (c): v cc = +1.8v to 5.5v t amb = 0 c to +70 c industr ial (i): v cc = +1.8v to 5.5v t amb = -40 c to +85 c a utomotiv e (e): v cc = +4.5v to 5.5v t amb = -40 c to 125 c p ar ameter symbol min max units conditions cloc k frequency f clk 100 100 400 khz 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v cloc k high time t high 4000 4000 600 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v cloc k lo w time t low 4700 4700 1300 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v sd a and scl r ise time ( note 1 ) t r 1000 1000 300 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v sd a and scl f all time ( note 1 ) t f 300 300 300 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v st ar t condition hold time t hd : sta 4000 4000 600 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v st ar t condition setup time t su : sta 4700 4700 600 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v data input hold time t hd : dat 0 ns ( note 2 ) data input setup time t su : dat 250 250 100 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v st op condition setup time t su : sto 4000 4000 600 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v wp setup time t su : wp 4000 4000 600 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v wp hold time t hd : wp 4700 4700 1300 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v output v alid from cloc k ( note 2 ) t aa 3500 3500 900 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v bus free time: time the b us m ust be free bef ore a ne w tr ansmission can star t t buf 4700 4700 1300 ns 4.5v v cc 5.5v (e t emp r ange) 1.8v v cc 2.5v 2.5v v cc 5.5v output f all time from vih minim um to v il maxim um t of 20 250 ns c b 100 pf ( note 1 ) input lter spik e suppression (sd a and scl pins) t sp 50 ns ( notes 1 and 3 ) wr ite cycle time (b yte or page) t wc 5 10 ms v cc 3 2.5v v cc < 2.5v endur ance 1m cycles 25 c , v cc = 5.0v , bloc k mode ( note 4 ) note 1: not 100% tested. c b = total capacitance of one b us line in pf . 2: as a tr ansmitter , the de vice m ust pro vide an inter nal minim um dela y time to br idge the unde ned region (minim um 300 ns) of the f alling edge of scl to a v oid unintended gener ation of st ar t or st op conditions . 3: the combined tsp and vh ys speci cations are due to ne w schmitt tr igger inputs which pro vide impro v ed noise spik e sup- pression. this eliminates the need f or a ti speci cation f or standard oper ation. 4: this par ameter is not tested b ut guar anteed b y char acter ization. f or endur ance estimates in a speci c application, please consult the t otal endur ance model which can be obtained on microchip s bbs or w ebsite .
24aa256/24lc256/24C256 ds21203a -page 4 preliminary ? 1997 microchip technology inc. 2.0 pin descriptions 2.1 a0, a1, a2 chip ad dress inputs the a0, a1, a2 inputs are used b y the 24xx256 f or m ul- tiple de vice oper ation. the le v els on these inputs are compared with the corresponding bits in the sla v e address . the chip is selected if the compare is tr ue . up to eight de vices ma y be connected to the same b us b y using diff erent chip select bit combinations . if left unconnected, these inputs will be pulled do wn inter- nally to v ss . 2.2 sd a serial data this is a bi-directional pin used to tr ansf er addresses and data into and data out of the de vice . it is an open dr ain ter minal, theref ore the sd a b us requires a pull-up resistor to v cc (typical 10 k w f or 100 khz, 2 k w f or 400 khz) f or nor mal data tr ansf er sd a is allo w ed to change only dur ing scl lo w . changes dur ing scl high are reser v ed f or indicating the st ar t and st op conditions . 2.3 scl serial cloc k this input is used to synchroniz e the data tr ansf er from and to the de vice . 2.4 wp this pin can be connected to either v ss , v cc or left oating. an inter nal pull-do wn on this pin will k eep the de vice in the unprotected state if left oating. if tied to v ss or left oating, nor mal memor y oper ation is enab led (read/wr ite the entire memor y 0000-7fff). if tied to v cc , write oper ations are inhibited. read oper ations are not aff ected. 3.0 functional description the 24xx256 suppor ts a bi-directional tw o-wire b us and data tr ansmission protocol. a de vice that sends data onto the b us is de ned as a tr ansmitter , and a de vice receiving data as a receiv er . the b us m ust be controlled b y a master de vice which gener ates the ser ial cloc k (scl), controls the b us access , and gener ates the st ar t and st op conditions while the 24xx256 w or ks as a sla v e . both master and sla v e can oper ate as a tr ansmitter or receiv er , b ut the master de vice deter- mines which mode is activ ated. 4.0 b us chara cteristics the f ollo wing b us pr otocol has been de ned: data tr ansf er ma y be initiated only when the b us is not b usy . dur ing data tr ansf er , the data line m ust remain stab le whene v er the cloc k line is high. changes in the data line while the cloc k line is high will be inter preted as a st ar t or st op condition. accordingly , the f ollo wing b us conditions ha v e been de ned ( figure 4-1 ). 4.1 bus not busy (a) both data and cloc k lines remain high. 4.2 star t data t ransf er (b) a high to lo w tr ansition of the sd a line while the cloc k (scl) is high deter mines a st ar t condition. all commands m ust be preceded b y a st ar t condition. 4.3 stop data t ransf er (c) a lo w to high tr ansition of the sd a line while the cloc k (scl) is high deter mines a st op condition. all oper ations m ust end with a st op condition. 4.4 data v alid (d) the state of the data line represents v alid data when, after a st ar t condition, the data line is stab le f or the dur ation of the high per iod of the cloc k signal. the data on the line m ust be changed dur ing the lo w per iod of the cloc k signal. there is one bit of data per cloc k pulse . each data tr ansf er is initiated with a st ar t condition and ter minated with a st op condition. the n umber of the data b ytes tr ansf erred betw een the st ar t and st op conditions is deter mined b y the master de vice . 4.5 ac kno wledg e each receiving de vice , when addressed, is ob liged to gener ate an ac kno wledge signal after the reception of each b yte . the master de vice m ust gener ate an e xtr a cloc k pulse which is associated with this ac kno wledge bit. a de vice that ac kno wledges m ust pull do wn the sd a line dur ing the ac kno wledge cloc k pulse in such a w a y that the sd a line is stab le lo w dur ing the high per iod of the ac kno wledge related cloc k pulse . of course , setup and hold times m ust be tak en into account. dur- ing reads , a master m ust signal an end of data to the sla v e b y no t gener ating an ac kno wledge bit on the last b yte that has been cloc k ed out of the sla v e . in this case , the sla v e ( 24xx256 ) will lea v e the data line high to enab le the master to gener ate the st op condition. note: the 24xx256 does not gener ate an y ac kno wledge bits if an inter nal prog r am- ming cycle is in prog ress .
24aa256/24lc256/24C256 ? 1997 microchip technology inc. preliminary ds21203a -page 5 figure 4-1: data t ransf er sequence on the serial bus figure 4-2: ac kno wledg e timing address or a ckno wledge v alid d a t a allo wed t o change st op condition st ar t condition scl sd a (a) (b) (d) (d) (c) (a) scl 9 8 7 6 5 4 3 2 1 1 2 3 t r ansmitter m ust release the sd a line at this point allo wing the receiv er to pull the sd a line lo w to ac kno wledge the pre vious eight bits of data. receiv er m ust release the sd a line at this point so the t r ansmitter can contin ue sending data. data from tr ansmitter data from tr ansmitter sd a ac kno wledge bit
24aa256/24lc256/24C256 ds21203a -page 6 preliminary ? 1997 microchip technology inc. 5.0 de vice ad dressing a control b yte is the rst b yte receiv ed f ollo wing the star t condition from the master de vice ( figure 5-1 ). the control b yte consists of a 4-bit control code; f or the 24xx256 this is set as 1010 binar y f or read and wr ite oper ations . the ne xt three bits of the control b yte are the chip select bits (a2, a1, a0). the chip select bits allo w the use of up to eight 24xx256 de vices on the same b us and are used to select which de vice is accessed. the chip select bits in the control b yte m ust correspond to the logic le v els on the corresponding a2, a1, and a0 pins f or the de vice to respond. these bits are in eff ect the three most signi cant bits of the w ord address . the last bit of the control b yte de nes the oper ation to be perf or med. when set to a one a read oper ation is selected, and when set to a z ero a wr ite oper ation is selected. the ne xt tw o b ytes receiv ed de ne the address of the rst data b yte ( figure 5-2 ). because only a14?0 are used, the upper address bit is a don? care bit. the upper address bits are tr ansf erred rst, f ol- lo w ed b y the less signi cant bits . f ollo wing the star t condition, the 24xx256 monitors the sd a b us chec king the control b yte being tr ansmitted. upon receiving a 1010 code and appropr iate de vice select bits , the sla v e de vice outputs an ac kno wledge signal on the sd a line . depending on the state of the r/ w bit, the 24xx256 will select a read or wr ite oper ation. figure 5-1: contr ol byte format 5.1 contiguous ad dressing acr oss multiple de vices the chip select bits a2, a1, a0 can be used to e xpand the contiguous address space f or up to 2 mbit b y adding up to eight 24xx256 's on the same b us . in this case , softw are can use a0 of the control b yte as address bit a15; a1, as address bit a16; and a2, as address bit a17. it is not possib le to read or wr ite across de vice boundar ies . figure 5-2: ad dress sequence bit assignments 1 0 1 0 a2 a1 a0 s a ck r/ w control code chip select bits sla v e address ac kno wledge bit star t bit read/ wr ite bit 1 0 1 0 a 2 a 1 a 0 r/w x a 11 a 10 a 9 a 7 a 0 a 8 a 12 contr ol byte address high byte address lo w byte contr ol code chip select bits x = don? care bit a 13 a 14
24aa256/24lc256/24C256 ? 1997 microchip technology inc. preliminary ds21203a -page 7 6.0 write opera tions 6.1 byte write f ollo wing the star t condition from the master , the con- trol code (f our bits), the chip select (three bits), and the r/ w bit (which is a logic lo w) are cloc k ed onto the b us b y the master tr ansmitter . this indicates to the addressed sla v e receiv er that the address high b yte will f ollo w after it has gener ated an ac kno wledge bit dur ing the ninth cloc k cycle . theref ore the ne xt b yte tr ansmit- ted b y the master is the high-order b yte of the w ord address and will be wr itten into the address pointer of the 24xx256 . the ne xt b yte is the least signi cant address b yte . after receiving another ac kno wledge sig- nal from the 24xx256 , the master de vice will tr ansmit the data w ord to be wr itten into the addressed memor y location. the 24xx256 ac kno wledges again and the master gener ates a stop condition. this initiates the inter nal wr ite cycle , and, dur ing this time , the 24xx256 will not gener ate ac kno wledge signals ( figure 6-1 ). if an attempt is made to wr ite to the arr a y with the wp pin held high, the de vice will ac kno wledge the command b ut no wr ite cycle will occur , no data will be wr itten, and the de vice will immediately accept a ne w command. after a b yte wr ite command, the inter nal address counter will point to the address location f ollo wing the one that w as just wr itten. 6.2 p a g e write the wr ite control b yte , w ord address , and the rst data b yte are tr ansmitted to the 24xx256 in the same w a y as in a b yte wr ite . but instead of gener ating a stop condi- tion, the master tr ansmits up to 63 additional b ytes , which are tempor ar ily stored in the on-chip page b uff er and will be wr itten into memor y after the master has tr ansmitted a stop condition. after receipt of each w ord, the six lo w er address pointer bits are inter nally incre- mented b y one . if the master should tr ansmit more than 64 b ytes pr ior to gener ating the stop condition, the address counter will roll o v er and the pre viously receiv ed data will be o v erwr itten. as with the b yte wr ite oper ation, once the stop condition is receiv ed, an inter- nal wr ite cycle will begin. ( figure 6-2 ). if an attempt is made to wr ite to the arr a y with the wp pin held high, the de vice will ac kno wledge the command b ut no wr ite cycle will occur , no data will be wr itten, and the de vice will immediately accept a ne w command subject to t buf . 6.3 write pr otection the wp pin allo ws the user to wr ite-protect the entire arr a y (0000-7fff) when the pin is tied to v cc . if tied to v ss or left oating, the wr ite protection is disab led. the wp pin is sampled at the st op bit f or e v er y wr ite com- mand ( figure 1-1 ) t oggling the wp pin after the st op bit will ha v e no eff ect on the e x ecution of the wr ite cycle . figure 6-1: byte write figure 6-2: p a g e write x b us a ctivity master sd a line b us a ctivity s t a r t contr ol byte address high byte address lo w byte d a t a s t o p a c k a c k a c k a c k x = don? care bit s 1 0 1 0 0 a 2 a 1 a 0 p x b us a ctivity master sd a line b us a ctivity s t a r t contr ol byte address high byte address lo w byte d a t a byte 0 s t o p a c k a c k a c k a c k d a t a byte 63 a c k x = don? care bit s 1 0 1 0 0 a 2 a 1 a 0 p
24aa256/24lc256/24C256 ds21203a -page 8 preliminary ? 1997 microchip technology inc. 7.0 a ckno wledge polling since the de vice will not ac kno wledge dur ing a wr ite cycle , this can be used to deter mine when the cycle is complete (this f eature can be used to maximiz e b us throughput.) once the stop condition f or a wr ite com- mand has been issued from the master , the de vice ini- tiates the inter nally timed wr ite cycle . a ck polling can be initiated immediately . this in v olv es the master send- ing a star t condition, f ollo w ed b y the control b yte f or a wr ite command (r/ w = 0). if the de vice is still b usy with the wr ite cycle , then no a ck will be retur ned. if no a ck is retur ned, then the star t bit and control b yte m ust be resent. if the cycle is complete , then the de vice will retur n the a ck, and the master can then proceed with the ne xt read or wr ite command. see figure 7-1 f or o w diag r am. figure 7-1: ac kno wledg e p olling flo w send wr ite command send stop condition to initiate wr ite cycle send star t send control byte with r/w = 0 did de vice ac kno wledge (a ck = 0)? ne xt oper ation no yes
24aa256/24lc256/24C256 ? 1997 microchip technology inc. preliminary ds21203a -page 9 8.0 read opera tion read oper ations are initiated in the same w a y as wr ite oper ations with the e xception that the r/ w bit of the control b yte is set to one . there are three basic types of read oper ations: current address read, r andom read, and sequential read. 8.1 current ad dress read the 24xx256 contains an address counter that main- tains the address of the last w ord accessed, inter nally incremented b y one . theref ore , if the pre vious read access w as to address n (n is an y legal address), the ne xt current address read oper ation w ould access data from address n + 1. upon receipt of the control b yte with r/ w bit set to one , the 24xx256 issues an ac kno wledge and tr ansmits the 8-bit data w ord. the master will not ac kno wledge the tr ansf er b ut does gener ate a stop condition and the 24xx256 discontin ues tr ansmission ( figure 8-1 ). figure 8-1: current ad dress read 8.2 random read random read oper ations allo w the master to access an y memor y location in a r andom manner . t o perf or m this type of read oper ation, rst the w ord address m ust be set. this is done b y sending the w ord address to the 24xx256 as par t of a wr ite oper ation (r/ w bit set to 0). after the w ord address is sent, the master gener ates a star t condition f ollo wing the ac kno wledge . this ter mi- nates the wr ite oper ation, b ut not bef ore the inter nal address pointer is set. then, the master issues the con- trol b yte again b ut with the r/ w bit set to a one . the 24xx256 will then issue an ac kno wledge and tr ansmit the 8-bit data w ord. the master will not ac kno wledge the tr ansf er b ut does gener ate a stop condition which causes the 24xx256 to discontin ue tr ansmission ( figure 8-2 ). after a r andom read command, the inter- nal address counter will point to the address location f ollo wing the one that w as just read. 8.3 sequential read sequential reads are initiated in the same w a y as a r an- dom read e xcept that after the 24xx256 tr ansmits the rst data b yte , the master issues an ac kno wledge as opposed to the stop condition used in a r andom read. this ac kno wledge directs the 24xx256 to tr ansmit the ne xt sequentially addressed 8-bit w ord ( figure 8-3 ). f ollo wing the nal b yte tr ansmitted to the master , the master will no t gener ate an ac kno wledge b ut will gen- er ate a stop condition. t o pro vide sequential reads , the 24xx256 contains an inter nal address pointer which is incremented b y one at the completion of each oper a- tion. this address pointer allo ws the entire memor y contents to be ser ially read dur ing one oper ation. the inter nal address pointer will automatically roll o v er from address 7fff to address 0000 if the master ac kno wl- edges the b yte receiv ed from the arr a y address 7fff . figure 8-2: random read figure 8-3: sequential read b us a ctivity master sd a line b us a ctivity p s s t o p contr ol byte s t a r t d a t a a c k n o a c k 1 1 0 0 a a a 1 byte 2 1 0 x b us a ctivity master sd a line b us a ctivity a c k n o a c k a c k a c k a c k s t o p s t a r t contr ol byte address high byte address lo w byte contr ol byte d a t a byte s t a r t x = don? care bit s 1 0 1 0 a a a 0 2 1 0 s 1 0 1 0 a a a 1 2 1 0 p b us a ctivity master sd a line b us a ctivity contr ol byte d a t a n d a t a n + 1 d a t a n + 2 d a t a n + x n o a c k a c k a c k a c k a c k s t o p p
24aa256/24lc256/24C256 ds21203a -page 10 preliminary ? 1997 microchip technology inc. notes:
24aa256/24lc256/24C256 ? 1997 microchip technology inc. preliminary ds21203a -page 11 24xx256 pr oduct identification system t o order or obtain inf or mation, e .g., on pr icing or deliv er y , ref er to the f actor y or the listed sales of ce . sales and suppor t p ac ka g e: p = plastic dip (300 mil body), 8-lead sm = plastic soic (208 mil body , eiaj standard), 8-lead t emperature rang e: blank = 0 c to +70 c i = -40 c to +85 c e = -40 c to -125 c de vice: 24aa256 256k bit 1.8v i 2 c ser ial eepr om 24aa256 t 256k bit 1.8v i 2 c ser ial eepr om (t ape and reel) 24lc256 256k bit 2.5v i 2 c ser ial eepr om 24lc256 t 256k bit 2.5v i 2 c ser ial eepr om (t ape and reel) 24C256 256k bit 5.0v i 2 c ser ial eepr om 24C256 t 256k bit 5.0v i 2 c ser ial eepr om (t ape and reel) 24xx256 /p data sheets products suppor ted b y a preliminar y data sheet ma y ha v e an err ata sheet descr ibing minor oper ational diff erences and recom- mended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: 1. y our local microchip sales of ce (see last page). 2. the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277. 3. the microchip s bulletin board, via y our local compuser v e n umber (compuser v e membership no t required). please specify which de vice , re vision of silicon and data sheet (include liter ature #) y ou are using.
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchips products as critical components in life sup port systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the m icrochip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds21203a-page 12 preliminary ? 1997 microchip technology inc. americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602-786-7200 fax: 602-786-7277 technical support: 602 786-7627 web: www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972-991-7177 fax: 972-991-8588 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714-263-1888 fax: 714-263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516-273-5305 fax: 516-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia paci? rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology india no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?n road west, hongiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 singapore microchip technology taiwan singapore branch 200 middle road #10-03 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2-717-7175 fax: 886-2-545-0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44-1628-851077 fax: 44-1628-850259 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 m?chen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleone palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-39-6899939 fax: 39-39-6899883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81-4-5471- 6166 fax: 81-4-5471-6122 06/16/97 printed on recycled paper.

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